A. Cervin, K. Årzén, and D. Henriksson, Control Loop Timing Analysis Using TrueTime and Jitterbug, Proceedings of the 2006 IEEE Conference on Computer Aided Control Systems Design (CACSD), 2006.

, Architecture Analysis & Design Language (AADL), SAE Standards: AS5506, P. Feiler, 2004.

K. J. Åström and B. Wittenmark, Computer Controlled Systems -Theory and Design, 1996.

M. Steenstrup, M. A. Arbib, and E. G. Manes, Port Automata and the Algebra of Concurrent Processes, Journal of Computer and System Sciences, vol.27, issue.1, pp.29-50, 1983.

P. Feiler and J. Hansson, Flow Latency Analysis with the Architecture Analysis and Design Language (AADL), 2007.

P. Caspi and O. Maler, On the Implementation of Control Loops by Software, 1574?1581. Proceedings of the 2006 IEEE Conference on Computer Aided Control Systems Design (CACSD), 2006.

P. Feiler, Efficient Embedded Runtime Systems Through Port Communication Optimization, Proceedings of the 13th IEEE International Conference on Engineering of Complex Computer Systems, 2008.

. Arinc, ARINC Specification 653P1-2. 653P1-2 Avionics Application Software Standard Interface, 2003.

, Architecture Analysis & Design Language (AADL) Version 2, SAE Standards: AS5506-2, P. Feiler, 2008.

, End-to-end timing analysis for gated networks, Symta Vision

, AADL: Architecture Analysis & Design Language ARINC: Aeronautical Radio Inc. CAN Bus: Controller Area Network Bus GALS: Globally asynchronous Locally Synchronous Systems ICO: Input-Compute-Output IMA: Integrated Modular Avionics PALS: Physically asynchronous Logically Synchronous Systems SAE: Society of Automotive Engineers