ADC Resolution Enhancement Based on Shannon Interpolation

Abstract : This paper exposes a method that gives us the possibility to use a low accuracy Analog - to - Digital Converter (ADC) in high - resolution measurements. We increase the resolution of a 12 - bits ADC to 16 - bits by adding sample s which are calculated using Shannon interpolate algorithm. Thus, t he digital signal has high resolution compared to measurements. Specific hardware architecture was developed to implement the algorithm in FPGA. The great adv antages of the proposed design are an enhancement of ADC resolution and the continuous time is modeled as a white noise which is generated by the FPGA itself, obviating the need of an external noise source . R esults were presented in order to confirm the method .
Type de document :
Article dans une revue
International Journal of Modern Sciences and Engineering Technology, 2016, 3 (1), pp.57-61
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https://hal-insu.archives-ouvertes.fr/insu-01352024
Contributeur : Nathalie Pothier <>
Soumis le : vendredi 5 août 2016 - 11:25:00
Dernière modification le : jeudi 7 février 2019 - 17:07:16

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  • HAL Id : insu-01352024, version 1

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Youssef Kebbati, A. Ndaw. ADC Resolution Enhancement Based on Shannon Interpolation. International Journal of Modern Sciences and Engineering Technology, 2016, 3 (1), pp.57-61. 〈insu-01352024〉

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