Improvement of The ADC Resolution Based onFPGA Implementation of Interpolating Algorithm

Abstract : This paper exposes a method that gives us the possibility to use a low accuracy Analog - to - Digital Converter (ADC) in high - resolution m easurements. We increase the resolution of a 12 - bits ADC to 16 - bits by adding samples which are calculated using Shannon interpolate algorithm. Thus, the digital signal has high resolution compared to measurements. Specific hardware architecture was develo ped to implement the algorithm in FPGA. The great advantages of the proposed design are an enhancement of ADC resolution and the continuous time is modeled as a white noise which is generated by the FPGA itself, obviating the need of an external noise sour ce. Results were presented in order to confirm the method
Type de document :
Article dans une revue
International Journal of New Technolog y and Research (IJNTR ), 2016, 2 (1), pp.100 - 103
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https://hal-insu.archives-ouvertes.fr/insu-01352020
Contributeur : Nathalie Pothier <>
Soumis le : vendredi 5 août 2016 - 11:20:11
Dernière modification le : jeudi 7 février 2019 - 17:06:13

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  • HAL Id : insu-01352020, version 1

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Youssef Kebbati, A. Ndaw. Improvement of The ADC Resolution Based onFPGA Implementation of Interpolating Algorithm. International Journal of New Technolog y and Research (IJNTR ), 2016, 2 (1), pp.100 - 103. 〈insu-01352020〉

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